Technische Universität Dresden

Sung-Mo “Steve” Kang

Contact Sung-Mo Kang
ORCID

Contact

Mailing address:
University of California, Santa Cruz
1156 High Street BE239
Santa Cruz, CA95064

Telephone: +1 831 502 7052

Mobile: +1 831 706 5456

Research Field and Activities

  • Memristive Devices and Systems
  • VLSI Design

Short Biography

Sung-Mo “Steve” Kang is a Distinguished Professor of Jack Baskin School of Engineering, UC Santa Cruz. He was the 15th president of Korea Advanced Institute of Science and Technology (KAIST) for February 2013-Februarey 2017; the 2nd Chancellor of the University of California, Merced for March 2007-June 2011; dean of engineering of the University of California, Santa Cruz for January 2001-February 2007; and department head of electrical and computer engineering at the University of Illinois at Urbana-Champaign for August 1995-December 2000.

Prior to returning to academia, he had led the development of world’s premier CMOS 32bit VLSI microprocessor chipsets for telecommunication and computing applications as a technical supervisor of AT&T Bell laboratories, Murray Hill, NJ. This historical achievement was celebrated with issuance of a US postage stamp.

For his research and education contributions, he has received numerous honors, including the Silicon Valley Engineering Hall of Fame induction, Alexander von Humboldt Senior US Scientists Award, IEEE Millennium Medal, IEEE Mac Van Valkenburg Circuits and Systems (CAS) Society Award, IEEE CAS Technical Excellence Award, the US Semiconductor Research Corporation (SRC) Technical Excellence Award, IEEE Graduate Teaching Technical Field Award, IEEE CAS John Choma Education Award, Chang-Lin Tien Education Leadership Award, and distinguished alumni awards from UC Berkeley, State University of New York at Buffalo, and Fairleigh Dickinson University and Yonsei University.

Kang is a fellow of IEEE, ACM, AAAS, a member of both the National Academy of Engineering, Korea and the Korea Academy of Science and Technology, and has served on the Presidential Advisory Council on Science and Technology of the Republic of Korea, and as chair of the World Economic Forum’s Global Agenda Council for Future of Electronics. He holds 16 US patents and has authored ten books and published over 500 journal and conference papers. He has obtained his Ph.D. from UC Berkeley, M.S. from State University of New York, Buffalo and B.S. (Summa Cum Laude) from Fairleigh Dickinson University, Teaneck, NJ. He was awarded an Honorary Doctor of Science from Fairleigh Dickinson University.

Dr. Kang’s current research interest includes low-power VLSI design, hardware-software synergy, compact modeling of novel devices, circuits and systems for computer-aided design, memristive electronics, and neuromorphic computing.

Publications

  • S. Shin, K. Kim, and S.M. Kang, “Memristor Applications for Programmable Analog ICs,” IEEE Transactions on Nanotechnology, vol. 10, no. 2, pp. 266-274, Jan. 2010. DOI: 10.1109/TNANO.2009.2038610
  • P. Mazumder, S.M. Kang, and R. Waser, “Memristors: Devices, Models, and Applications,” Proceedings of the IEEE, vol. 100, no. 6, pp. 1911-1919, June 2012. DOI: 10.1109/JPROC.2012.2190812
  • S. Shin, L. Zheng, K. Kim, and S.M. Kang, “Memristive Trans-Impedance Amplifier (mTIA) and Its Application to DNA Sequencing,” 4th Memristors and Memristive Symposium (CNNA), pp. 1-2, Notre Dame, IN, July 2014.
  • “Memristor-based Ternary Content Addressable Memory (mTCAM),” IEEE International Symposium on Circuits and Systems (ISCAS’14), pp. 2253-2256, Melbourne, Australia, 2014. DOI: 10.1109/ISCAS.2014.6865530
  • J. K., K.-R. Cho, H.C. Lu, T. Fernando, N. Iannella, S.M. Kang, and K. Eshraghian, “Maximization of Crossbar Array Memory Using Fundamental Memristor Theory,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 64, no. 12, pp. 1402-1406, Dec. 2017. DOI: 10.1109/TCSII.2017.2767078.
  • W. Welch, T. Yu, S.M. Kang, and J. Sax, “Computer Experiments for Quality Control by Parameter Design,” Journal of Quality Technology, vol. 22, no. 1, pp. 15-22, Jan. 1990. DOI: 10.1080/00224065.1990.11979201.
  • S. Sapatnekar, V.B. Rao, P.M. Vaidya, and S.M. Kang, “An Exact Solution to the Transistor Sizing Problem for CMOS Circuits Using Convex Optimization,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 12, no. 11, pp. 1621-1634, Nov. 1993. DOI: 10.1109/43.248073
  • S.M. Kang, “Accurate Simulation of Power Dissipation in VLSI Circuits,” IEEE Journal of Solid-State Circuits, vol. 21, no. 5, pp. 889-891, Oct. 1986.