Technische Universität Dresden

Shahar Kvatinsky

Revolutionize computer architecture and systems by integrating emerging technologies in a non-conventional manner.

Contact Shahar Kvatinsky
ORCID

Contact

Prof. Shahar Kvatinsky
Andrew and Erna Viterbi Faculty of
Electrical & Computer Engineering
Technion – Israel Institute of Technology
Haifa 3200003
Israel

Email:shahar@ee.technion.ac.il

Telephone:+972 73 378 71 79

Research Field and Activities

  • Circuit design
  • Computer architecture
  • VLSI systems
  • Neuromorphic computing
  • Artificial Intelligence
  • Hardware security

Short Biography

Shahar Kvatinsky is an assistant professor at the Andrew and Erna Viterbi Faculty of Electrical Engineering, Technion – Israel Institute of Technology. He received the B.Sc. degree in computer engineering and applied physics and an MBA degree in 2009 and 2010, respectively, both from the Hebrew University of Jerusalem, and the Ph.D. degree in electrical engineering from the Technion – Israel Institute of Technology in 2014. From 2006 to 2009 he was with Intel as a circuit designer and was a post-doctoral research fellow at Stanford University from 2014 to 2015. Kvatinsky is an editor in Microelectronics Journal and has been the recipient of the 2015 IEEE Guillemin-Cauer Best Paper Award, 2015 Best Paper of Computer Architecture Letters, Viterbi Fellowship, Jacobs Fellowship, the 2014 and 2017 Hershel Rich Technion Innovation Awards, 213 Standford Kaplan Prize for Creative Management in High Tech, 2010 Benin prize, and six Technion excellence teaching awards. His current research is focused on circuit and architectures with emerging memory technologies and design of energy efficient architectures.

References

  • S. Kvatinsky, E. G. Friedman, A. Kolodny, and U. C. Weiser, “TEAM – ThrEshold Adaptive Memristor Model,” IEEE Transactions on Circuits and Systems I: Regular Papers, Vol. 60, No. 1, pp. 211-221, January 2013. Link​

  • S. Kvatinsky, E. G. Friedman, A. Kolodny, and U. C. Weiser, “The Desired Memristor for Circuit Designers,” IEEE Circuits and Systems Magazine, Vol. 13, No. 2, pp. 17-22, second quarter 2013. Link​

  • S. Kvatinsky, N. Wald, G. Satat, E. G. Friedman, A. Kolodny, and U. C. Weiser, “Memristor-Based Material Implication (IMPLY) Logic: Design Principles and Methodologies,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 22, No. 10, pp. 2054-2066, October 2014. Link​

  • S. Kvatinsky, D. Belousov, S. Liman, G. Satat, N. Wald, E. G. Friedman, A. Kolodny, and U. C. Weiser, “MAGIC – Memristor Aided LoGIC,” IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. 61, No. 11, pp. 895-899, November 2014. Link

  • S. Kvatinsky, M. Ramadan, E. G. Friedman, and A. Kolodny, “VTEAM – A General Model for Voltage Controlled Memristor,” IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. 62, No. 8, pp. 786-790, August 2015. Link​

  • S. Kvatinsky, Y. H. Nacson, Y. Etsion, E. G. Friedman, A. Kolodny, and U. C. Weiser, “Memristor-Based Multithreading,” IEEE Computer Architecture Letters, Vol. 13, No. 1, pp. 41-44, January-June 2014. Link​

  • S. Kvatinsky, N. Wald, G. Satat, E. G. Friedman, A. Kolodny, and U. C. Weiser, “MRL – Memristor Ratioed Logic,” Proceedings of the International Cellular Nanoscale Networks and their Applications, pp. 1-6, August 2012. Link​

  • S. Kvatinsky, E. G. Friedman, A. Kolodny, and U. C. Weiser, “Memristor-based IMPLY Logic Design Flow,” Proceedings of the IEEE International Conference on Computer Design, pp. 142-147, October 2011. Link​

  • S. Kvatinsky, E. G. Friedman, A. Kolodny, and L. Schächter, “Power Grid Analysis Based on a Macro Circuits Model,” Proceedings of the IEEE Convention of Electrical and Electronics Engineers in Israel, pp. 708-712, November 2010. Link​

  • S. Kvatinsky, A. Kolodny, and U. C. Weiser, “Memristor-Based Multithreading,” US Patent Application No. 10521237. Link​