Chua Memristor CenterProf. Qiangfei Xia
Department of Electrical and Computer Engineering
University of Massachusetts Amherst
Email: qxia@umass.edu
Professor Qiangfei Xia is the Dev and Linda Gupta Professor of Electrical and Computer Engineering at the University of Massachusetts Amherst. He is internationally recognized for his pioneering work in memristive devices, neuromorphic computing, and in-memory processing. His research focuses on building nanoscale electronic systems that mimic the brain’s computing efficiency and enable next-generation artificial intelligence hardware.
He earned his Ph.D. in Electrical Engineering from Princeton University and previously worked at HP Labs in Palo Alto, where he contributed significantly to the development of memristor technology. At UMass Amherst, he leads the Nanoelectronics Group, exploring cutting-edge innovations in nanoelectronics, resistive memory (RRAM), and AI accelerators.
Dr. Xia received a DARPA Young Faculty Award, an NSF CAREER award, the Barbara H. and Joseph I. Goldstein Outstanding Junior Faculty Award, an Outstanding Senior Faculty Award, and the Chancellor’s Medal (the highest recognition bestowed upon faculty by UMass Amherst). He is a “Highly Cited Researcher” according to Clarivate, and an IEEE Fellow “for contributions to resistive memory arrays and devices for in-memory computing.”
Y. Huang, T. Ando, A. Sebastian, M.-F. Chang, J. J. Yang, and Q. Xia, “Memristor-based hardware accelerators for artificial intelligence,” Nature Reviews Electrical Engineering, vol. 1, pp. 286–299, 2024. DOI: https://doi.org/10.1038/s44287-024-00037-6
W. Song, M. Rao, Y. Li, C. Li, Y. Zhuo, M. Wu, W. Yin, Z. Li, Q. Wei, S. Lee, H. Zhu, L. Gong, M. Barnell, Q. Wu, P. A. Beerel, M. S.-W. Chen, N. Ge, M. Hu, Q. Xia, and J. J. Yang, “Programming memristor arrays with arbitrarily high precision for analog computing,” Science, vol. 383, pp. 903–910, 2024. DOI: https://doi.org/10.1126/science.adi9405
P. Lin, C. Li, Z. Wang, Y. Li, H. Jiang, W. Song, M. Rao, Y. Zhuo, N. K. Upadhyay, M. Barnell, Q. Wu, J. J. Yang, and Q. Xia, “Three-dimensional memristor circuits as complex neural networks,” Nature Electronics, vol. 3, pp. 225–232, 2020. DOI: https://doi.org/10.1038/s41928-020-0397-9
Q. Xia and J. J. Yang, “Memristive crossbar arrays for brain-inspired computing,” Nature Materials, vol. 18, p. 309, 2019. DOI: https://doi.org/10.1038/s41563-019-0291-x
S. Pi, C. Li, H. Jiang, W. Xia, H. L. Xin, J. J. Yang, and Q. Xia, “Memristor crossbar arrays with 6-nm half-pitch and 2-nm critical dimension,” Nature Nanotechnology, vol. 14, pp. 35–39, 2019. DOI: https://doi.org/10.1038/s41565-018-0302-0
H. Jiang, C. Li, R. Zhang, P. Yan, P. Lin, Y. Li, J. J. Yang, D. Holcomb, and Q. Xia, “A provable key destruction scheme based on memristor crossbar arrays,” Nature Electronics, vol. 1, pp. 548–554, 2018. DOI: https://doi.org/10.1038/s41928-018-0146-5
C. Li, M. Hu, Y. Li, H. Jiang, N. Ge, E. Montgomery, J. Zhang, W. Song, N. Dávila, C. E. Graves, Z. Li, J. P. Strachan, P. Lin, Z. Wang, M. Barnell, Q. Wu, R. S. Williams, J. J. Yang, and Q. Xia, “Analogue signal and image processing with large memristor crossbars,” Nature Electronics, vol. 1, pp. 52–59, 2018. DOI: https://doi.org/10.1038/s41928-017-0002-z
Z. Wang, S. Joshi, S. E. Savel’ev, H. Jiang, R. Midya, P. Lin, M. Hu, N. Ge, J. P. Strachan, Z. Li, Q. Wu, M. Barnell, G. L. Li, H. L. Xin, R. S. Williams, Q. Xia, and J. J. Yang, “Memristors with diffusive dynamics as synaptic emulators for neuromorphic computing,” Nature Materials, vol. 16, pp. 101–108, 2017. DOI: https://doi.org/10.1038/nmat4756
H. Jiang, L. Han, P. Lin, Z. Wang, M. Jang, Q. Wu, M. Barnell, J. J. Yang, H. L. Xin, and Q. Xia, “Sub-10 nm Ta channel responsible for superior performance of a HfO₂ memristor,” Scientific Reports, vol. 6, p. 28525, 2016. DOI: https://doi.org/10.1038/srep28525
Q. Xia, W. Robinett, M. W. Cumbie, N. Banerjee, T. J. Cardinali, J. J. Yang, W. Wu, X. M. Li, W. M. Tong, D. B. Strukov, G. S. Snider, G. Medeiros-Ribeiro, and R. S. Williams, “Memristor-CMOS hybrid integrated circuits for reconfigurable logic,” Nano Letters, vol. 9, pp. 3640–3645, 2009. DOI: https://doi.org/10.1021/nl901874j
