Technische Universität Dresden
Faculty of Electrical and Computer Engineering
Institute of Circuits and Systems
Chair of Fundamentals of Electrical Engineering

ioannis.messaris@tu-dresden.de

Ioannis Messaris received his Diploma in Physics and his MSc in Electronic Physics from the Aristotle University of Thessaloniki (AUTH), Greece in 2008 and 2013 respectively. He is currently in pursuit of his PhD in Electronic Physics (AUTH) which involves the development of models for simulating nanoscale transistor and memristor-based circuits.

From 2013 – 2016 he was a research associate of 2 separate scientific groups in the Department of Physics, AUTH Thessaloniki which developed a) reliability models for Fin-shaped Field Effect Transistors (FInFETs) and b) analytical models for planar nanoscale combinational digital cells. In 2017 he worked as a short-term scientific collaborator with the Electronics and Computer Science (ECS) dept., University of Southampton where he developed simulation models and parameter extraction algorithms for Resistive Random Access Memory devices. Since 2018 he is a research associate in the Faculty of Electrical and Computer Engineering, Technische Universität Dresden investigating the complex behavior of memristor-equipped Cellular Neural Networks. Since 2017 he is journal and conference reviewer for IEEE TNANO, IEEE TCAS II, IJCTA, IEEE IEDM, IEEE ISCAS and IEEE ICECS.

1. I. Messaris, A. Serb, S. Stathopoulos, A. Khiat, S. Nikolaidis, and T. Prodromakis, “A data-driven verilog-A ReRAM model,” IEEE Trans. Comput. Des. Integr. Circuits Syst., 2018.
2. I. Messaris, C. Galani, M. Ntogramatzi, N. Karagiorgos, P. Chaourani, A. Tzormpatzoglou, S. Goudos, and S. Nikolaidis, “An Evaluation of the Equivalent Inverter Modeling Approach,” Circuits, Syst. Signal Process., 2017.
3. I. Messaris, T. A. Karatsori, N. Fasarakis, C. G. Theodorou, S. Nikolaidis, G. Ghibaudo, and C. A. Dimitriadis, “Hot carrier degradation modeling of short-channel n-FinFETs suitable for circuit simulators,” Microelectron. Reliab., vol. 56, 2016.

1. I. Messaris, A. Ascoli, G. Meinhardt, R. Tetzlaff and L. O. Chua, “Mem-computing CNNs with bistable-like memristors” in 2019 IEEE International Symposium on Circuits and Systems (ISCAS), 2019, accepted for presentation.
2. A. Ascoli, I. Messaris, R. Tetzlaff and L. O. Chua, “CNNs with bistable-like non-volatile memristors: a novel mem-computing paradigm for the IoT era,” in 2018 25th IEEE International Conference on Electronics, Circuits and Systems (ICECS), 2018, in press.
3. I. Messaris, M. Ntogramatzi and S. Nikolaidis, “A Voltage-Controlled Window Function Approach,” ANNA ’18; Advances in Neural Networks and Applications 2018, St. Konstantin and Elena Resort, Bulgaria, 2018, pp. 1-5.
4. S. Goudos, N. Karagiorgos, M. Ntogramatzi, I. Messarisand S. Nikolaidis, “Evaluation of an Artificial Neural Network Approach for Timing Modeling of CMOS Gates,” 2018 28th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS), Platja d’Aro, 2018, pp. 169-176.
5. A. Serb, E. Manino, I. Messaris, L. Tran-Thanh, and T. Prodromakis, “Hardware-level Bayesian inference,” in Neural Information Processing Systems, 2017.
6. C. de Benito, M. M. A. Chawa, J. L. Rossello, M. Roca, R. Picos, I. Messaris, and S. Nikolaidis, “An analytical delay model for ReRAM memory cells,” in 2017 27th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS), 2017, pp. 1–6.
7. I. Messaris, A. Serb, S. Stathopoulos, I. Gupta, A. Khiat, S. Nikolaidis and T. Prodromakis, “A TiO2 ReRAM parameter extraction method,” in 2017 IEEE International Symposium on Circuits and Systems (ISCAS), 2017, p. 1-4.
8. I. Messaris, S. Nikolaidis, A. Serb, S. Stathopoulos, I. Gupta, A. Khiat, and T. Prodromakis, “Live demonstration: A TiO2 ReRAM parameter extraction method,” in 2017 IEEE International Symposium on Circuits and Systems (ISCAS), 2017, p. 1.
9. C. Galani, A. Tsormpatzoglou, P. Chaourani, I. Messaris, and S. Nikolaidis, “A study for replacing CMOS gates by equivalent inverters,” in Proceedings – IEEE International Symposium on Circuits and Systems, 2015, vol. 2015–July.
10. I. Messaris, N. Fasarakis, T. A. Karatsori, A. Tsormpatzoglou, G. Ghibaudo, and C. A. Dimitriadis, “Hot carrier degradation modeling of short-channel n-FinFETs,” in Device Research Conference – Conference Digest, DRC, 2015, vol. 2015–August, pp. 183–184.
11. P. Chaourani, I. Messaris, N. Fasarakis, M. Ntogramatzi, S. Goudos, and S. Nikolaidis, “An analytical model for the CMOS inverter,” in 2014 24th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2014, 2014.
12. I. Messaris, N. Karagiorgos, P. Chaourani, and S. Nikolaidis, “Static Gate Power Consumption Model based on Power Contributors,” Des. Circuits Integr. Systems (DCIS), 2014 Conf., pp. 1–5, 2014.