Technische Universität Dresden

dietmar fey


Prof. Dr.-Ing. Dietmar Fey
FAU Erlangen-Nürnberg
Department Informatik
Martensstraße 3
91058 Erlangen

tel: +49 9131 85-27003

fax: +49 9131 85-27912


Research Field and Activities

  •  Using non-volatile memory technology (memristors) for embedded AI
  • Design of AI accelerator cores
  • Systolic arrays architectures for neuromorphic accelerators
  • Digital control of neuromorphic hardware
  • Evaluation AI-based procedures for radar signal processing for automotive applications
  • Design of FPGA- and ASIC-based controllers for electronic ortheses

Short Biography

Prof. Dr.-Ing. Dietmar Fey is distinguished professor in the field of Computer Science, currently leading the Chair of Computer Architecture at Friedrich-Alexander-University (FAU) Erlangen-Nürnberg, Germany. His academic journey began at FAU, where he earned his diploma degree in Computer Science and later his Ph.D. in 1992. His doctoral work focused on an investigation about using optics in computer architectures. From 1994 to 1999, he researched at Friedrich-Schiller-University Jena where he completed his habilitation. He then worked as a lecturer at Universität Siegen before becoming a Professor for Computer Engineering at University Jena.

Throughout his illustrious career, Prof. Fey has been an active participant in numerous national and international research projects, particularly in the areas of parallel and embedded computing. He contributed to the nationwide priority Program “SPP 1188 – Organic Computing” and was a principal investigator in Ph.D. student elite Research Training Group on “Heterogeneous Image Systems”, both funded by the German Research Foundation (DFG). He also contributed to the Project “Interchip Optical Communications and Photonic PCBs for next generation OBP” funded by the European Space Agency (ESA) and collaborated with industrial partners on Grid and Cloud Computing technology.

References / Teachings

  1. T. Baumeister, F. Schmutterer, and D. Fey, “From Myths to Methods: Teaching Cryptography with the Enigma Machine,” 7th International Conference on Historical Cryptology (HistoCrypt 2024), Oxford, 2024. DOI: 10.58009/aere-perennius0084.
  2. F. Ebrahimiazandaryani and D. Fey, “ExTern: Boosting RISC-V core performance using ternary encoding,” Microprocessors and Microsystems, vol. 107, Art. No.: 105058, 2024. DOI: 10.1016/j.micpro.2024.105058.
  3. T. Baumeister, P. Rambach, and D. Fey, “The Benefits of Continuous Assessment: A Case Study on the Effectiveness of Weekly Online Quizzes in Computer Science Courses,” 16th International Conference of Education, Research and Innovation, Seville, 2023. DOI: 10.21125/iceri.2023.1161.
  4. D. Fey, “Memristive computing in Germany,” it – Information Technology, 2023. DOI: 10.1515/itit-2023-0017.
  5. K. Gündogan, P. Gündisch, and D. Fey, “Heterogeneous Framework Architecture of Specialized Accelerators for Vehicle Sensors,” AmE 2023 – Automotive meets Electronics; 14th GMM Symposium 2023. [Online]. Available:
  6. M. Hoffmann, T. Noegel, C. Schüßler, L. Schwenger, P. Gulden, D. Fey, and M. Vossiek, “Implementation of Real-Time Automotive SAR Imaging,” 20th European Radar Conference, Berlin, 2023. DOI: 10.23919/EuRAD58043.2023.10289475.
  7. S. Hosseinzadeh Foroushani, M. Klemm, G. Fischer, and D. Fey, “Optimizing multi-level ReRAM memory for low latency and low energy consumption,” it – Information Technology, 2023. DOI: 10.1515/itit-2023-0022.
  8. S. Hosseinzadeh, A. Parvaresh, and D. Fey, “Optimization of OLAP In-Memory Database Management Systems with Processing-In-Memory Architecture,” 36th International Conference on Architecture of Computing Systems, ARCS 2023, Athens, GRC, 2023. DOI: 10.1007/978-3-031-42785-5_18.
  9. J. Kliemt and D. Fey, “Work in Progress: Extending Virtual Prototypes of Microprocessor Architectures with Accuracy Tracing,” 13th International Conference on Simulation and Modeling Methodologies, Technologies and Applications, Rome, 2023. DOI: 10.5220/0012131800003546.
  10. Jr. Reuben, D. Fey, S. Lancaster, and S. Slesazeck, “A Low-Power Ternary Adder Using Ferroelectric Tunnel Junctions,” Electronics, vol. 12, Art. No.: 1163, 2023. DOI: 10.3390/electronics12051163.