Technische Universität Dresden

Shahar Kvatinsky

Revolutionize computer architecture and systems by integrating emerging technologies in a non-conventional manner.

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Prof. Shahar Kvatinsky
Andrew and Erna Viterbi Faculty of
Electrical & Computer Engineering
Technion – Israel Institute of Technology
Haifa 3200003
Israel

Email:shahar@ee.technion.ac.il

Telephone:+972 73 378 71 79

website

Research Field and Activities

  • Circuit design
  • Computer architecture
  • VLSI systems
  • Neuromorphic computing
  • Artificial Intelligence
  • Hardware security

Short Biography

Shahar Kvatinsky is a Full Professor at the Andrew and Erna Viterbi Faculty of Electrical and Computer Engineering, Technion – Israel Institute of Technology and a Visiting Professor at the Edward S. Rogers Sr. Department of Electrical & Computer Engineering, University of Toronto. Shahar received the B.Sc. degree in Computer Engineering and Applied Physics and an MBA degree in 2009 and 2010, respectively, both from the Hebrew University of Jerusalem, and the Ph.D. degree in Electrical Engineering from the Technion – Israel Institute of Technology in 2014. From 2006 to 2009, he worked as a circuit designer at Intel. From 2014 to 2015, he was a post-doctoral research fellow at Stanford University. Kvatinsky is a member of the Israel Young Academy and a Fellow of the Young Academy of Europe. He is the head of the Architecture and Circuits Research Center at the Technion, chair of the IEEE Circuits and Systems in Israel, and an associate editor of Microelectronics Journal. Kvatinsky has been the recipient of numerous awards: the 2023 Uzi & Michal Halevy Award for Innovative Applied Engineering, the 2021 Norman Seiden Prize for Academic Excellence, the 2020 MDPI Electronics Young Investigator Award, the 2019 Wolf Foundation’s Krill Prize for Excellence in Scientific Research, the 2015 IEEE Guillemin-Cauer Best Paper Award, the 2015 Best Paper of Computer Architecture Letters, Viterbi Fellowship, Jacobs Fellowship, an ERC starting grant, the 2017 Pazy Memorial Award, 2014, 2017, 2021, and 2025 Hershel Rich Technion Innovation Awards, the 2013 Sanford Kaplan Prize for Creative Management in High Tech, 2010 Benin prize, and seven Technion excellence teaching awards. His current research is focused on circuits and architectures with emerging memory technologies and the design of energy-efficient architectures.

References

  • S. Kvatinsky, E. G. Friedman, A. Kolodny, and U. C. Weiser, “TEAM – ThrEshold Adaptive Memristor Model,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 60, no. 1, pp. 211–221, Jan. 2013. DOI: https://doi.org/10.1109/TCSI.2012.2215714
  • S. Kvatinsky, E. G. Friedman, A. Kolodny, and U. C. Weiser, “The Desired Memristor for Circuit Designers,” IEEE Circuits and Systems Magazine, vol. 13, no. 2, pp. 17–22, Q2 2013. DOI: https://doi.org/10.1109/MCAS.2013.2256257
  • S. Kvatinsky, N. Wald, G. Satat, E. G. Friedman, A. Kolodny, and U. C. Weiser, “Memristor-Based Material Implication (IMPLY) Logic: Design Principles and Methodologies,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 22, no. 10, pp. 2054–2066, Oct. 2014. DOI: https://doi.org/10.1109/TVLSI.2013.2294916
  • S. Kvatinsky, D. Belousov, S. Liman, G. Satat, N. Wald, E. G. Friedman, A. Kolodny, and U. C. Weiser, “MAGIC – Memristor Aided LoGIC,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 61, no. 11, pp. 895–899, Nov. 2014. DOI: https://doi.org/10.1109/TCSII.2014.2357292
  • S. Kvatinsky, M. Ramadan, E. G. Friedman, and A. Kolodny, “VTEAM – A General Model for Voltage Controlled Memristor,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 62, no. 8, pp. 786–790, Aug. 2015. DOI: https://doi.org/10.1109/TCSII.2015.2433531
  • S. Kvatinsky, Y. H. Nacson, Y. Etsion, E. G. Friedman, A. Kolodny, and U. C. Weiser, “Memristor-Based Multithreading,” IEEE Computer Architecture Letters, vol. 13, no. 1, pp. 41–44, Jan.–Jun. 2014. DOI: https://doi.org/10.1109/L-CA.2013.3
  • S. Kvatinsky, N. Wald, G. Satat, E. G. Friedman, A. Kolodny, and U. C. Weiser, “MRL – Memristor Ratioed Logic,” in Proceedings of the 13th International Workshop on Cellular Nanoscale Networks and Their Applications (CNNA 2012), pp. 1–6, Aug. 2012. DOI: https://doi.org/10.1109/CNNA.2012.6331426
  • S. Kvatinsky, E. G. Friedman, A. Kolodny, and U. C. Weiser, “Memristor-Based IMPLY Logic Design Flow,” in Proceedings of the IEEE International Conference on Computer Design (ICCD 2011), pp. 142–147, Oct. 2011. DOI: https://doi.org/10.1109/ICCD.2011.6081389
  • S. Kvatinsky, E. G. Friedman, A. Kolodny, and L. Schächter, “Power Grid Analysis Based on a Macro Circuits Model,” in Proceedings of the IEEE Convention of Electrical and Electronics Engineers in Israel (IEEEI 2010), pp. 708–712, Nov. 2010. DOI: https://doi.org/10.1109/EEEI.2010.5662121